One type of conventional transmitter circuit includes a serializer circuit. The serializer circuit includes X-to-2 multiplexer circuits, a 2-to-1 multiplexer circuit, and a frequency divider circuit. An X number of input data signals are provided in parallel to multiplexing inputs of the X-to-2 multiplexer circuit. Parallel data bits are embodied in the input data signals.
Complementary input clock signals are provided through a clock network to inputs of a buffer circuit. The buffer circuit buffers the input clock signals to generate complementary output clock signals that are ideally 180° out of phase. The buffer circuit includes 6 inverter circuits. The first and second inverter circuits in the buffer circuit are connected together in series. The first and second inverter circuits buffer a first one of the input clock signals received at an input of the first inverter circuit to generate a first one of the output clock signals at an output of the second inverter circuit. The third and fourth inverter circuits in the buffer circuit are connected together in series. The third and fourth inverter circuits buffer a second one of the input clock signals received at an input of the third inverter circuit to generate a second one of the output clock signals at an output of the fourth inverter circuit.
The fifth and sixth inverter circuits in the buffer circuit are cross-coupled inverter circuits. The input of the fifth inverter circuit is connected to the output of the first inverter circuit, to the input of the second inverter circuit, and to the output of the sixth inverter circuit. The output of the fifth inverter circuit is connected to the output of the third inverter circuit, to the input of the fourth inverter circuit, and to the input of the sixth inverter circuit.
The output clock signals are provided to inputs of the frequency divider circuit and to select inputs of the 2-to-1 multiplexer circuit. The frequency divider circuit generates complementary frequency divided clock signals in response to the output clock signals. The frequency of each of the frequency divided clock signals is a fraction of the frequency of one of the output clock signals.
The X-to-2 multiplexer circuits provide the data bits in the input data signals to their outputs as even and odd data signals in response to the frequency divided clock signals. The X-to-2 multiplexer circuits provide half of the data bits in the input data signals as serial data bits in the even data signal. The X-to-2 multiplexer circuits provide the other half of the data bits in the input data signals as serial data bits in the odd data signal. The even data signal contains data bits in the even numbered unit intervals of the input data signals, and the odd data signal contains data bits in the odd numbered unit intervals of the input data signals. The even and odd data signals are provided to multiplexing inputs of the 2-to-1 multiplexer circuit.
The 2-to-1 multiplexer circuit converts the even and odd data signals into a single output data signal containing a serial stream of data bits in response to the output clock signals. The output data signal includes the data bits from the even data signal interleaved with the data bits from the odd data signal. The serial data bits in the output data signal can be represented as EOEOEOEOE . . . , where bits E are from the even data signal, and bits O are from the odd data signal.
The 2-to-1 multiplexer circuit includes two registers. The outputs of the two registers are coupled to the output of the 2-to-1 multiplexer circuit that generates the output data signal. The first register stores data bits in the even data signal at the output of the 2-to-1 multiplexer circuit in the output data signal in response to rising edges in the first one of the output clock signals. The second register stores data bits in the odd data signal at the output of the 2-to-1 multiplexer circuit in the output data signal in response to rising edges in the second one of the output clock signals. The transmitter circuit transmits the output data signal to a receiver circuit.
The output clock signals should have 50% duty cycles. Duty cycle typically refers to the ratio between the duration of a logic high state in a signal and the period of the signal. The frequencies of the output clock signals equal one-half the data rate of the output data signal. The output clock signals may have duty cycle distortion (DCD). DCD causes the duty cycle of a periodic signal to vary from an ideal value. DCD causes the duty cycle of the output clock signals to be greater than or less than 50%. DCD may be caused, for example, by variations between the pull-up currents and the pull-down currents generated by transistors in the clock network. DCD in the output clock signals is dependent on variations in the process, the supply voltage, and the temperature of the transmitter circuit.
Duty cycle distortion (DCD) in the output clock signals may cause the 2-to-1 multiplexer circuit to generate data dependent jitter in the output data signal. Jitter in the output data signal may cause the receiver circuit to sample incorrect data bits in the output data signal.
As an example, DCD can cause the first one of the input clock signals to have a phase offset with respect to the second one of the input clock signals that is greater than 180°. The input clock signals are ideally 180° out of phase with each other. The buffer circuit described above can prevent phase offsets that are within about 5-10% of the periods of the input clock signals from propagating to the output clock signals. However, process variations that cause mismatches between the transistors in the fifth and sixth inverter circuits in the buffer circuit may add additional DCD to the output clock signals.
As another example, DCD can cause each of the rising edges of the first one of the input clock signals to occur in less time than each of the falling edges of the first one of the input clock signals. DCD can also cause each of the falling edges of the second one of the input clock signals to occur in less time than each of the rising edges of the second one of the input clock signals. The duty cycles of the input clock signals are less than 50% in this example. The buffer circuit described above does not prevent this type of DCD in the input clock signals from propagating to the output clock signals.